When the most important interface in a computer system is the instruction set architecture (ISA) as it connects software to hardware, have you wondered why the ISA is still proprietary? Especially since there are open standards for almost all other important interfaces? The best architectural style for any free, open ISA just may be RISC.
You can hear more about these issues, plus enter to win free Neo data, at the next Silicon Valley IoT Meetup. Join us on October 27, 2015, in Mountain View, CA, for this discussion, networking, and a Neo prize drawing.
For our last Meetup of the year, our presenter is Professor Krste Asanović from the EECS Department at the University of California, Berkeley. He will lead a discussion about the RISC-V Instruction Set Architecture, open source ISAs, and IoT. RISC-V (pronounced "risk-five") is a new instruction set architecture that was originally designed to support computer architecture research and education, and it could become a standard open architecture for industry implementations. RISC-V was first developed at Berkeley. Professor Asanović leads the free RISC-V ISA project, is chairman of the RISC-V Foundation, and has recently co-founded SiFive Inc. to support commercial use of RISC-V processors. You can learn more about RISC-V here.
RSVP for the Meetup
To attend this Meetup on the topic, "Instruction Sets Should Be Free: The Case For RISC-V," please RSVP at our Meetup page. The event takes place on Tuesday, October 27, and starts at 6:30pm.
We're also happy to announce a raffle giveaway. Three lucky attendees will win a three-month package of free Neo connectivity ($25 value) for your IoT devices. Make sure you stay for the drawing. Hope to see you there!